1. Field
The disclosure presented herein relates to pulsed signaling systems, and more particularly to a multiplexer for use in a pulsed signaling system.
2. Description of the Related Art
Power dissipation is an important factor affecting high-speed signaling rates. A useful metric in this context involves a ratio of milliwatts (mW) expended per gigabits-per-second (Gbps) of signaling rate. As an example, a high-performance signaling system may consume 30 mW/Gbps per signaling interface. For a sixteen-bit wide memory interface running at 3.2 Gbps, the total power of the signaling interface may exceed 1500 mW, on both the memory controller and memory device sides of the interface.
To minimize link interface power, those skilled in the art have proposed using capacitively-coupled interconnects (CCI) to carry out capacitively-coupled pulse signaling (CCPS). In this signaling scheme, power dissipates during signal transitions—i.e., during the “AC” portion of the signal. Unlike most other types of common electrical signaling (eg, non-return-to-zero, or “NRZ” signaling), little to no power dissipates during the “DC” portion of the signal. This results in a dramatic decrease in the mW/Gbps metric described above.
What is needed and as yet unavailable are improvements in CCI and CCPS circuits and methods to enable high-speed signaling in low power memory systems. The architectures and methods described herein satisfy this need.